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HTG13J0 4-bit microcontroller 1 may 19, 1999 general description the HTG13J0 is a processor from holtek s 4-bit stand alone single chip microcontroller specially designed for lcd product applica - tions. it is especially suited for applications re - quiring low power consumption system with many lcd segments, such as calculator, scale, subsystem controller, hand-held lcd products and electronic appliances. features operating voltage: 2.4v~3.3v eight input lines three output lines five working registers rc oscillator for system clock 8k 8 program rom 160 4 data ram 40 8 segment lcd driver, 1/5 bias, 1/8 duty 8-bit programmable timer with built-in fre - quency source internal timer overflow interrupt 16 kinds of programmable sound effect one-level subroutine nesting halt function and wake up feature reduce power consumption halt instruction 8-bit table read instruction up to 4.0 m sec instruction cycle (1.0mhz system clock), at v dd =3v 96 powerful instructions
block diagram notes: acc: accumulator pc: program counter r0~r4: working registers pa0~pa2: output port pp, ps: input ports pa3: rom bank switch ht13j0 2 may 19, 1999 alu acc stack pc rom pa0 pa1 pa2 bz lc d d river seg 0 seg 1 seg 2 seg 38 seg 39 com 1 com 7 com 0 r0 r1 r2 r3 r4 osci osco test1 test2 vdd vss t1d s ound e ffe c t ps pp pa tim er pp0 pp1 pp2 pp3 ps0 ps1 ps2 pa3 tem porary data ram d isplay d ata r a m instruction d ecoder c ontrol and tim ing circuit res bz ps3
pad assignment chip size: 2746 3552 ( m m) 2 * the ic substrate should be connected to vss in the pcb layout artwork. ht13j0 3 may 19, 1999 1 36 2 37 3 38 4 39 5 40 6 41 7 42 8 43 9 44 10 45 11 46 12 47 13 48 14 49 15 50 16 51 17 52 18 53 19 54 20 55 21 56 22 57 23 58 24 59 25 60 26 61 27 62 28 63 29 64 30 65 31 66 32 67 33 68 34 69 35 70 (0,0) bz bz vdd osci osco t512 com7 com6 com5 com4 com3 com2 com1 com0 test1 test2 ps2 ps1 ps0 vss seg37 seg38 seg39 res pp3 pp2 pp1 pp0 pa0 pa1 pa2 ps3 t1d seg18 seg19 seg20 seg21 seg22 seg23 seg24 seg25 seg26 seg27 seg28 seg29 seg30 seg31 seg32 seg33 seg34 seg35 seg36 seg17 seg16 seg15 seg14 seg13 seg12 seg11 seg10 seg9 seg8 seg7 seg6 seg5 seg4 seg3 seg2 seg1 seg0
pad coordinates unit: m m pad no. x y pad no. x y 1 - 1244.25 1523.47 36 1244.25 - 1080.67 2 - 1244.25 1256.62 37 1244.25 - 936.67 3 - 1203.75 1017.25 38 1244.25 - 792.67 4 - 1244.25 861.97 39 1244.25 - 648.67 5 - 1244.25 353.02 40 1244.25 - 504.67 6 - 1244.25 227.02 41 1244.25 - 360.67 7 - 1244.25 101.03 42 1244.25 - 216.68 8 - 1244.25 - 24.98 43 1244.25 - 72.68 9 - 1244.25 - 150.98 44 1244.25 71.32 10 - 1244.25 - 276.98 45 1244.25 215.32 11 - 1244.25 - 402.98 46 1244.25 359.33 12 - 1244.25 - 528.97 47 1244.25 503.33 13 - 1244.25 - 654.97 48 1244.25 729.22 14 - 1244.25 - 780.97 49 1244.25 882.22 15 - 1244.25 - 906.97 50 1244.25 1035.22 16 - 1244.25 - 1032.97 51 1244.25 1188.22 17 - 1244.25 - 1158.97 52 1244.25 1341.22 18 - 1244.25 - 1284.97 53 1228.95 1617.53 19 - 1244.25 - 1410.97 54 1084.95 1617.53 20 - 1206.45 - 1617.53 55 954.45 1617.53 21 - 923.85 - 1556.78 56 823.95 1617.53 22 - 671.40 - 1568.47 57 693.45 1617.53 23 - 469.35 - 1556.78 58 562.95 1617.53 24 - 217.35 - 1556.78 59 432.45 1617.53 25 22.95 - 1556.78 60 301.95 1617.53 26 232.20 - 1617.53 61 171.45 1617.53 27 371.70 - 1617.53 62 40.95 1617.53 28 511.20 - 1617.53 63 - 89.55 1617.53 29 650.70 - 1617.53 64 - 220.05 1617.53 30 790.20 - 1617.53 65 - 350.55 1617.53 31 929.70 - 1617.53 66 - 481.05 1617.53 32 1069.20 - 1617.53 67 - 611.55 1617.53 33 1208.70 - 1617.53 68 - 742.05 1617.53 34 1244.25 - 1361.03 69 - 872.55 1617.53 35 1244.25 - 1224.67 70 - 1003.05 1617.53 ht13j0 4 may 19, 1999
pad description pad no. pad name i/o mask option description 1 2 bz bz o * sound effect output 3 vdd i ? positive power supply 4 5 osci osco i o ? osci, osco are connected to resistor for in - ternal system clock. 6 15 16 21 t512 test1 test2 t1d o i i o ? for test mode only test1 and test2 must be open when the chip is in normal operation (with internal pull high resistor). 7~14 com7~com0 o ? output for lcd panel common plate 17~19 22 ps2~ps0 ps3 i pull-high or none ** 4-bit port for input only 20 vss i ? negative power supply, gnd 23~25 pa2~pa0 o cmos or nmos open drain 3-bit latch port for output only 26~29 pp0~pp3 i pull-high or none ** 4-bit port for input only 30 res i ? input to reset lsi reset is active at logical low level. 31~70 seg39~seg0 o ? lcd driver outputs for lcd panel segment *: 6 internal sources deriving from system clock can be selected as sound effect clock by mask op- tion. if holtek s sound library is invoked, only 128k and 64k is accepted. **: each bit of input ports ps, pp can be a trigger source of halt interrupt. that can be specified by mask option. absolute maximum ratings supply voltage ............................. - 0.3v to 5.5v storage temperature ................ - 50 c to 125 c input voltage ................v ss - 0.3v to v dd +0.3v operating temperature ..................0 c to 70 c note: these are stress ratings only. stresses exceeding the range specified under "absolute maxi - mum ratings" may cause substantial damage to the device. functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged expo - sure to extreme conditions may affect device reliability. ht13j0 5 may 19, 1999
d.c. characteristics ta=25 c symbol parameter test conditions min. typ. max. unit v dd conditions v dd operating voltage ?? 2.4 ? 3.3 v i dd operating current 3v no load, f sys =500khz ? 200 500 m a i stb standby current 3v system halt ?? 1 m a v il1 input low voltage ps, pp 3v ? 0 ? 0.6 v v ih1 input high voltage ps, pp 3v ? 2.1 ? 3.0 v v il2 input low voltage res 3v ? 0 ? 0.6 v v ih2 input high voltage res 3v ? 2.6 ? 3.0 v i ol1 port a, bz and bz output sink current 3v v dd =3v, v ol =0.3v 1.5 3.0 ? ma i oh1 port a, bz and bz output source current 3v v dd =3v, v oh =2.7v - 0.8 - 1.5 ? ma i ol2 segment 0~7 output sink current 3v v lcd =3v, v ol =0.3v 80 130 ?m a i oh2 segment 0~7 output source current 3v v lcd =3v, v oh =2.7v - 50 - 90 ?m a i ol3 segment 8~39 output sink current 3v v lcd =3v, v ol =0.3v 40 80 ?m a i oh3 segment 8~39 output source current 3v v lcd =3v, v oh =2.7v - 30 - 60 ?m a i ol4 common sink current 3v v lcd =3v, v ol =0.3v 60 120 ?m a i oh4 common source current 3v v lcd =3v, v oh =2.7v - 60 - 120 ?m a r ph pull-high resistance 3v ps, pp, res 50 ? 300 k w ht13j0 6 may 19, 1999
a.c. characteristics ta=25 c symbol parameter test conditions min. typ. max. unit v dd conditions f sys system clock 3v r:680k w ~5k w 32 ? 1000 khz f lcd lcd clock 3v ?? 512* ? hz t com lcd common period ? 1/8 duty ? (1/f lcd ) 8 ? sec t cy cycle time ? f sys =1.0mhz ? 4.0 ?m s t res reset pulse width ?? 5 ?? ms f sound sound effect clock ?? ? 64 or 128 ** ? khz *: in general, f lcd is selected and optimized by holtek according to f sys and operating voltage. **: only these two clock signal frequencies are supported by the holtek sound library. ht13j0 7 may 19, 1999
ht13j0 8 may 19, 1999 mode program counter pa3 pc11 pc10 pc9 pc8 pc7 pc6 pc5 pc4 pc3 pc2 pc1 pc0 initial reset 10 0 0000000 0 0 0 internal interrupt pa3 0 0 0 0 0 0 0 0 0 1 0 0 external interrupt pa3 0 0 0 0 0 0 0 0 1 0 0 0 jump, call instruction pa3 pc11 pc10 pc9 pc8 pc7 pc6 pc5 pc4 pc3 pc2 pc1 pc0 conditional branch pa3 @ pc10 pc9 pc8 pc7 pc6 pc5 pc4 pc3 pc2 pc1 pc0 return from subroutine pa3 s11 s10 s9 s8 s7 s6 s5 s4 s3 s2 s1 s0 program counter notes: pc11~pc0: instruction code bits @: pc11 keeps the current value s11~s0: stack register bits pa3: bank value bits functional description program counter - pc the bit 13 of program memory is controlled by pa3 which can change the address of the pro - gram. there are two banks of the program memory, which are selected by pa3, every bank is 4kb rom. the instruction "ut pa,a" is used to change the value of pa3. then, low or high 4k rom is selected accordingly. all instruc - tions are not effective on crossing bank, unless the value of pa3 is changed in advance. the 12-bit program counter (pc) controls the sequence in which the instructions stored in program rom are executed and its contents specify a maximum of 4096 addresses. after accessing a memory word to fetch an in - struction code, the contents of the program counter are incremented by 1 or 2, then the pro - gram counter will point to the memory word containing the next instruction code. when executing the jump instruction (jmp, jnz, jc,jtmr...), subroutine call, internal in - terrupt, external interrupt or return from sub - routine, the pc manipulates the program transfer by loading the address corresponding to each instruction.
ht13j0 9 may 19, 1999 program memory - rom the program memory is used to store program instruction which is to be executed. it is orga - nized with 8192 8 bits and addressed by the program counter and pa3. certain locations in bank 0 of the program memory are reserved for specific usage: location 0004h this area are reserved for timer interrupt service program. a timer interrupt resulting from timer overflow, if interrupt is enabled the cpu begins execution at location 0004h. location 0008h activating the ps or pp input pins of the pro - cessor with the interrupts enabled during halt mode causes the program to jump to this location. location 0n00h~0nffh (n=current number) and 0f00h~0fffh. the last 256 bytes of each page in the pro - gram memory, addressed from 0n00h to 0nffh and 0f00h to 0fffh can be used as a look up table. the instructions read r4a, read mr0a, readf r4a, readf mr0a can read the table and transfer the contents of the table to acc and r4 or transfer to acc and data memory addressed by register pair r1,r0 . these area may function as normal program memory depending on the require- ment. note that the page number n must be greater than zero, some locations in page 0 are reserved for specific usage as mentioned. certain locations in bank 1 of the program memory are reserved for specific usage: location 1000h this area are reserved for the initialization program. after reset, the cpu always begins execution at location 1000h. location 1004h this area is reserved for timer interrupt service program. a timer interrupt resulting from timer overflow, if interrupt is enabled, the cpu begins execution at location 1004h. location 1008h activating the ps or pp input pins of the pro - cessor with the interrupts enabled during halt mode causes the program to jump to this location. location 1n00h~1nffh (n=current number) and 1f00h~1fffh. the last 256 bytes of each page in the pro - gram memory, addressed from 1n00h to 1nffh and 1f00h to 1fffh can be used as a loop up table. the instructions read r4a, read mr0a, readf r4a, readf mr0a can read the table and transfer the contents of the table to acc and r4 or transfer to acc and data memory addressed by register pair "r1,r0" these area may function as normal program memory depending on the require - ment. note that the page number n must be greater than zero, some locations in page 1 are reserved for specific usage as mentioned. the program memory (rom) mapping is shown below: 0000h 0003h 0007h 0f00h 0fffh 0004h 0008h 000bh 1000h 1003h 1007h 1f00h 1fffh 1004h 1008h 100bh program rom timer interrupt subroutine of bank 0 external interrupt subroutine of bank 0 page n look-up table (256 bytes) of bank 0 page f look-up table (256 bytes) of bank 0 reset initial program timer interrupt subroutine of bank 1 external interrupt subroutine of bank 1 page look-up table (256 bytes) of bank 1 page f look-up table (256 bytes) of bank 1 8bits program memory
ht13j0 10 may 19, 1999 in the execution of an instruction, the program counter is added before the executing phase. so a careful manipulation of read mr0a and read r4a is needed in the page margin. stack register the stack register is a group of registers used to save the contents of the program counter (pc) and is arranged in 13 bits 1 level. one bit is used to store the carry flag. an interrupt will force the contents of the pc and the carry flag onto the stack register. a subroutine call will also cause the pc contents to be pushed onto the stack; however the carry flag will not be stored. at the end of a subroutine or an inter - rupt (indicated by a return instruction ret or reti), the contents of the stack register are re - turned to the pc. executing "reti" instruction will restore the carry flag from the stack register, but "ret" does not. working registers - r0,r1,r2,r3,r4 these five registers are usually used to store the frequently accessed data. the working reg - ister can be incremented (+1) or decremented ( - 1). the jnz rn, address (n=0,1,4) instruction makes efficient use of the working register as a program loop counter. also the register pairs of r1, r0 and r3, r2 can be used as the data mem- ory pointer, when the data memory transfer in- struction is executed. data memory - ram the data memory is a static ram organized with 256 4 bit format and is used to store tem - porary data and display data. all of the data memory locations are indirectly addressable through the register pair "r1,r0" or "r3,r2". there are two areas in the data memory, tempo - rary data area and display data area. access to the temporary data memory is made through 00h - 9fh address, and access to the display data memory is made through b0h - ffh ad - dress. the locations between the temporary and display data areas are undefined and cannot be used. when data is written in the display area, the lcd driver automatically reads it and gene-rates an lcd driving signal. accumulator - acc the register acc plays the most important role in data manipulation and data transfer. it is not only one of the sources of input to the alu but also the destination of the result due to alu. data transfer can be performed between acc and other registers, data memory or i/o ports. arithmetic and logic unit - alu this circuit performs arithmetic and logic oper- ation. the alu provides the following func- tions: arithmetic operation (add, adc, sub, sbc, daa) logic operation (and, or, xor) rotation (rl, rr, rlc, rrc) increment and decrement (inc, dec) branch decision (jz, jnz, jc, jnc...) the alu not only outputs the results of data operation but also sets the status of carry flag (c) in some instructions. timer this is a programmable 8-bit count-up counter internal frequency sources to aid the user in counting and generate accurate time base. 4 bits temporary data area (160 x 4) undefined area display data area (80x4) 00h a0h b0h ffh data ram data memory
ht13j0 11 may 19, 1999 the timer is presettable and readable with software instructions. "timer xxh", "mov tmrl,a" and "mov tmrh,a" preload timer value. "mov a,tmrl" and "mov a,tmrh" read the contents of the timer to acc. the timer is stopped by a hardware reset or "timer off" instruction and started by a timer on instruction. once the timer is started, it will increment to its maximum count (ffh) and overflow to zero (00h) and will not stop until there is a timer off instruction or reset. when an overflow oc - curs, it will set the timer flag (tf) simulta - neously. if interrupt is enabled, the timer circuit supports tf for internal interrupt. the state of the tf is also testable with conditional instruc - tion jtmr. the timer flag is cleared after the interrupt or jtmr instruction is executed. the frequency of internal frequency source can be selected by mask option. m = 2 n where n=0, 1, 2......13 except 6, by mask option (the sixth stage is reserved for internal use). interrupt the HTG13J0 provide both internal and exter- nal interrupt modes. the di and ei instruc- tions are used to disable and enable the interrupts. during halt mode, if the pp or ps input pin is triggered on a high to low transition in the enable interrupt mode and the program is not within a call subroutine the external interrupt is activated. this causes a subroutine call to location 8 and resets the interrupt latch. likewise when the timer flag is set in the en - able interrupt mode and the program is not within a call subroutine, the internal inter - rupt is activated. this causes a subroutine call to location 4 and resets the timer flag. when running under a call subroutine or di, the interrupt acknowledge is on hold until the ret or ei instruction is invoked. the call in - struction should not be used within an inter - rupt routine as unpredictable result may occur. if within a call subroutine, an interrupt oc - curs, the interrupt will be serviced after leaving the call subroutine. the interrupts are disabled by a hardware re - set or a di instruction. they remain disabled until the ei instruction is executed. each input port pin can be programmed by mask option to have an external interrupt func - tion in the halt mode. initial reset the HTG13J0 provide a res pin for system ini - tialization. since the res pin has internal pull high resistor, only an external 0.1 m ~1 m capacitor is needed. if the reset pulse is generated exter - nally, it must be held low for at least 5 ms. when res is active, the internal block will be initialized as follows: pa3 and pc 1000h timer stop timer flag reset (low) sound sound off and one sing mode output port a high (or floating state) interrupt disabled bz and bz output high level halt this is a special feature of HTG13J0. it will stop the chip s normal operation and reduce power consumption. when the instruction halt is executed, then either of the following will occur: the system clock will be stopped the contents of the on-chip ram and regis - ters remain unchanged lcd segments and commons keep vdd volt - age (i.e. lcd becomes blank) the system can leave the halt mode by ways of initial reset or external interrupt and wake-up from the following entry of the pro - gram counter value.
ht13j0 12 may 19, 1999 initial reset: 1000h. interrupt (enabled): 1008h or 0008h. interrupt (disabled): next address of halt in - struction. in halt mode, each bit of ports pp, ps, can be used as external interrupt by mask option to wake-up the system. this signal is active in low-going transition. sound effect HTG13J0 provides sound effect circuit which offers up to 16 sounds with 3 effects of tone, boom and noise. holtek supports a sound li - brary which have melody, alarm, machine gun shooting, etc. that can meet various require - ments. whenever the instruction "sound n" or "sound a" is executed, the specified sound be - gin playing. whenever "sound off" is exe - cuted, it terminates the singing sound immediately. there are two singing mode, sone mode and sloop mode, this is activated by "sound one" and "sound loop". in sone mode, the sound that has been specified plays just once. in sloop mode, the sound being speci- fied keeps playing repeatedly. since sound 0~11 contain 32 notes, sound 12~15 contain 64 notes, the later possess better sound than the former. the frequency of sound effect circuit can be se- lected by mask option. m = 2 m where m=0, 1, 2, 3, 4, 5 the holtek s sound library only supports sound clock frequency 128k or 64k. if it is de - sired to utilize holtek s sound library, proper system clock and mask option should be se - lected. lcd display memory as mentioned in the data memory section, the lcd display memory is embedded in the data memory. it can be read and written to as nor - mal data memory. the following figure shows the mapping be - tween display memory and lcd pattern. to turn on/off the display, the programmer just writes 1/0 to the corresponding bit of the dis- play memory. the lcd display module may have any form as long as the number commons is no more than 8 and the segment is no more than 40. lcd driver output the output number of the lcd driver is 40 8. that can directly drive an lcd with 1/8 duty cycle and 1/5 bias. all lcd segments are ran- dom at the initial clear mode. the bias voltage circuit of the lcd display is built-in. no external resistor is needed. the lcd driving clock frequency shall be fixed in 512hz. that can not be selected by the user, and holtek will set it according to the applica - tion. com 0 1 2 3 4 5 6 7 display memory ffh fdh fbh f9h b5 b3 b1 feh fch fah f8h b4 b2 b0 bit 0 1 2 3 0 1 2 3 segment 0123 37 38 39 lcd display memory
ht13j0 13 may 19, 1999 an example of an lcd driving waveform (1/8 duty and 1/5 bias) is shown below. oscillator circuit only one external resistor is needed for HTG13J0 oscillator circuit. the system clock is also used as the reference sig - nal of lcd driving clock, sound effect clock, and internal timer frequency source. one HTG13J0 machine cycle consists of a se - quence of 4 states numbered t1 to t4. each state lasts for one oscillator period. the machine cycle is 4 m s, if the system frequency is up to 1.0mhz. input ports ps, pp all ports can have internal pull high resistors determined by mask option. every bit of the in - put ports pp and ps can be specified to be a trigger source to wake up the halt interrupt by mask option. a high to low transition on one of these pins will wake up the device from a halt status. output port pa0~pa2 a mask option is available to select whether the output is a cmos or open drain nmos type. after an initial clear, the output port pa de - faults high for cmos or floating for nmos. note: pa3 controls bit 13 of the program memory. be careful about pa3. when instruction "out p a,a" is operated, port a is changed as well. mask option the following options are available by mask op- tion which must be selected prior to manufac- turing. each bit of input ports ps, pp with or without pull-high resistor. each bit of input ports ps, pp function as halt interrupt trigger. each bit of output port pa0~pa2 with cmos or open drain nmos. 8 bit programmable timer with internal fre - quency sources. there are 13 (the sixth stage is reserved for internal use) internal fre - quency sources which can be selected as clocking signal. six kinds of sound clock frequency: f sys /2 m , m=0, 1, 2, 3, 4, 5 123456781234 vdd 4/5 vdd 3/5 vdd 2/5 vdd 1/5 vdd gnd com0 512hz 64hz 5 com1 seg0 vdd 4/5 vdd 3/5 vdd 2/5 vdd 1/5 vdd gnd vdd 4/5 vdd 3/5 vdd 2/5 vdd 1/5 vdd gnd d ck q q mask option internal bus vdd output port - pa0~pa2 vdd internal bus wake-up pull-high mask option read control wake-up mask option -
application circuits r*: depends on the required system clock frequency (r=680k w ~5k w , at v dd =3v) ht13j0 14 may 19, 1999 osci osco output po rt lcd p a tte rn (1/5 b ias, 1/8 d uty) pp3 pp2 pp1 pp0 pa0 pa1 pa2 in p u t po rt in p u t po rt com 0 com 1 output seg m ent x 40 com 7 bz ps0 ps1 ps2 res r* h tg 13j0 0.1 m f~1 m f ps3 bz
ht13j0 15 may 19, 1999 instruction set summary mnemonic description byte cycle cf arithmetic add a,[r1r0] adc a,[r1r0] sub a,[r1r0] sbc a,[r1r0] add a,xh sub a,xh daa add data memory to acc add data memory with carry to acc subtract data memory from acc subtract data memory from acc with borrow add immediate data to acc subtract immediate data from acc decimal adjust acc for addition 1 1 1 1 2 2 1 1 1 1 1 2 2 1 ? ? ? ? ? ? ? logic operation and a,[r1r0] or a,[r1r0] xor a,[r1r0] and [r1r0],a or [r1r0],a xor [r1r0],a and a,xh or a,xh xor a,xh and data memory to acc or data memory to acc exclusive-or data memory to acc and acc to data memory or acc to data memory exclusive-or acc to data memory and immediate data to acc or immediate data to acc exclusive-or immediate data to acc 1 1 1 1 1 1 2 2 2 1 1 1 1 1 1 2 2 2 ? ? ? ? ? ? ? ? ? increment and decrement inc a inc rn inc [r1r0] inc [r3r2] dec a dec rn dec [r1r0] dec [r3r2] increment acc increment register increment data memory increment data memory decrement acc decrement register decrement data memory decrement data memory 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 ? ? ? ? ? ? ? ? data move mov a,rn mov rn,a mov a,[r1r0] mov a,[r3r2] mov [r1r0],a mov [r3r2],a mov a,xh mov r1r0,xxh mov r3r2,xxh mov r4,xh move register to acc move acc to register move data memory to acc move data memory to acc move acc to data memory move acc to data memory move immediate data to acc move immediate data to r1 and r0 move immediate data to r3 and r2 move immediate data to r4 1 1 1 1 1 1 1 2 2 2 1 1 1 1 1 1 1 2 2 2 ? ? ? ? ? ? ? ? ? ?
ht13j0 16 may 19, 1999 mnemonic description byte cycle cf rotate rl a rlc a rr a rrc a rotate acc left rotate acc left through the carry rotate acc right rotate acc right through the carry 1 1 1 1 1 1 1 1 ? ? ? ? input and output in a,pi out pa,a input port-i to acc, port-i=ps,pp output acc to port-a 1 1 1 1 ? ? branch jmp addr jc addr jnc addr jtmr addr jan addr jz a,addr jnz a,addr jnz rn,addr jump unconditional jump on carry=1 jump on carry=0 jump on timer out jump on acc bit n=1, n=0,1,2,3 jump on acc is zero jump on acc is not zero jump on register rn not zero, n=0,1,4 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 ? ? ? ? ? ? ? ? subroutine call addr ret reti subroutine call return from subroutine or interrupt return from interrupt service routine 2 1 1 2 1 1 ? ? ? flag clc stc ei di nop clear carry flag set carry flag enable interrupt disable interrupt no operation 1 1 1 1 1 1 1 1 1 1 0 1 ? ? ? timer timer xxh timer on timer off mov a,tmrl mov a,tmrh mov tmrl,a mov tmrh,a set 8 bits immediate data to timer set timer start counting set timer stop counting move low nibble of timer to acc move high nibble of timer to acc move acc to low nibble of timer move acc to high nibble of timer 2 1 1 1 1 1 1 2 1 1 1 1 1 1 ? ? ? ? ? ? ?
ht13j0 17 may 19, 1999 mnemonic description byte cycle cf table read read r4a read mr0a readf r4a readf mr0a read rom code of current page to r4 and acc read rom code of current page to m(r1,r0),acc read rom code of page f to r4 and acc read rom code of page f to m(r1,r0),acc 1 1 1 1 2 2 2 2 ? ? ? ? sound control sound n sound a sound one sound loop sound off active sound channel n active sound channel with accumulator turn on sound one mode turn on sound repeat mode turn off sound 2 1 1 1 1 2 1 1 1 1 ? ? ? ? ? miscellaneous halt enter power down mode 2 2 ?
ht13j0 18 may 19, 1999 instruction definitions adc a,[r1r0] add data memory contents and carry to accumulator machine code 0 0 0 0 1 0 0 0 description the contents of the data memory addressed by the register pair "r1,r0" and carry are added to the accumulator. carry is affected. operation acc ? acc+m(r1,r0)+c add a,xh add immediate data to accumulator machine code 0 1 0 0 0 0 0 0 0 0 0 0 d d d d description the specified data is added to the accumulator. carry is affected. operation acc ? acc+xh add a,[r1r0] add data memory contents to accumulator machine code 0 0 0 0 1 0 0 1 description the contents of the data memory addressed by the register pair r1,r0" is added to the accumulator. carry is affected. operation acc ? acc+m(r1,r0) and a,xh logical and immediate data to accumulator machine code 0 1 0 0 0 0 1 0 0 0 0 0 d d d d description data in the accumulator is logical and with the immediate data speci - fied by code. operation acc ? acc "and" xh and a,[r1r0] logical and accumulator with data memory machine code 0 0 0 1 1 0 1 0 description data in the accumulator is logical and with the data memory addressed by the register pair "r1,r0". operation acc ? acc "and" m(r1,r0) and [r1r0],a logical and data memory with accumulator machine code 0 0 0 1 1 1 0 1 description data in the data memory addressed by the register pair "r1,r0" is logical and with the accumulator operation m(r1,r0) ? m(r1,r0) "and" acc
ht13j0 19 may 19, 1999 call address subroutine call machine code 1 1 1 1 a a a a a a a a a a a a description the program counter bits 0 1 1 are saved in the stack. the program coun - ter is then loaded from the directly-specified address. operation stack ? pc+2 pc ? address clc clear carry flag machine code 0 0 1 0 1 0 1 0 description the carry flag is reset to 0 operation c ? 0 daa decimal adjust accumulator machine code 0 0 1 1 0 1 1 0 description the accumulator value is adjusted to the bcd (binary code decimal) code, if the contents of the accumulator is greater than 9 or c (carry flag) is 1. operation if acc>9 or cf=1 then acc ? acc+6, c ? 1 else acc ? acc, c ? c dec a decrement accumulator machine code 0 0 1 1 1 1 1 1 description data in the accumulator is decremented by 1. carry flag is not affected. operation acc ? acc 1 dec rn decrement register machine code 0 0 0 1 n n n 1 description data in the working register "rn" is decremented by 1. carry flag is not affected. operation rn ? rn 1; rn=r0, r1, r2, r3, r4, for n=0, 1, 2, 3, 4 dec [r1r0] decrement data memory machine code 0 0 0 0 1 1 0 1 description data in the data memory specified by the register pair "r1,r0" is decre - mented by 1. carry flag is not affected. operation m(r1,r0) ? m(r1,r0) 1
ht13j0 20 may 19, 1999 dec [r3r2] decrement data memory machine code 0 0 0 0 1 1 1 1 description data in the data memory specified by the register pair "r3,r2" is decre - mented by 1. carry flag is not affected. operation m(r3,r2) ? m(r3,r2) - 1 di disable interrupt machine code 0 0 1 0 1 1 0 1 description internal time-out interrupt and external interrupt are disabled. ei enable interrupt machine code 0 0 1 0 1 1 0 0 description internal time-out interrupt and external interrupt are enabled. halt halt system clock machine code 0 0 1 1 0 1 1 1 0 0 1 1 1 1 1 0 description turn off system clock, and enter power down mode. operation pc ? (pc)+1 in a,pi input port to accumulator machine code 0 0 1 1 0 0 1 1 ps 0 0 1 1 0 1 0 0 pp description the data on port "pi" is transferred to the accumulator. operation acc ? pi; pi=ps or pp inc a increment accumulator machine code 0 0 1 1 0 0 0 1 description data in the accumulator is incremented by 1. carry flag is not affected. operation acc ? acc+1 inc rn increment register machine code 0 0 0 1 n n n 0 description data in the working register "rn" is incremented by 1. carry flag is not affected. operation rn ? rn+1; rn=r0, r1, r2, r3, r4 for n=0, 1, 2, 3, 4 inc [r1r0] increment data memory machine code 0 0 0 0 1 1 0 0 description data in the data memory specified by the register pair "r1,r0" is incre - mented by 1. carry flag is not affected. operation m(r1,r0) ? m(r1,r0)+1
ht13j0 21 may 19, 1999 inc [r3r2] increment data memory machine code 0 0 0 0 1 1 1 0 description data memory specified by the register pair "r3,r2" is incremented by 1. carry flag is not affected. operation m(r3,r2) ? m(r3,r2)+1 jan address jump if accumulator bit n is set machine code 1 0 0 n n a a a a a a a a a a a description bits 0~10 of the program counter are replaced with the directly-specified address, bit 11 of the program counter and pa3 of the memory bank re - main, if accumulator bit n is set to 1. operation pc (bit 0~10) ? address, if acc bit n=1 (n=0,1,2,3,) pc ? pc+2, if acc bit n=0 jc address jump if carry is set machine code 1 1 0 0 0 a a a a a a a a a a a description bits 0~10 of the program counter are replaced with the directly-specified address, bit 11 of the program counter and pa3 of the memory bank re - main, if c (carry flag) is set to 1. operation pc (bit 0~10) ? address, if c=1 pc ? pc+2, if c=0 jmp address direct jump machine code 1 1 1 0 a a a a a a a a a a a a description bits 0~11 of the program counter are replaced with the directly-specified address. operation pc ? address jnc address jump if carry is not set machine code 1 1 0 0 1 a a a a a a a a a a a description bits 0~10 of the program counter are replaced with the directly-specified address, bit 11 of the program counter and pa3 of the memory bank re- main, if c (carry flag) is set to 0. operation pc (bit 0~10) ? address, if c=0 pc ? pc+2, if c=1
ht13j0 22 may 19, 1999 jnz a,address jump if accumulator is not 0 machine code 1 0 1 1 1 a a a a a a a a a a a description bits 0~10 of the program counter are replaced with the directly-specified address, bit 11 of the program counter and pa3 of the memory bank re - main, if the accumulator is not 0. operation pc (bit 0~10) ? address, if acc 1 0 pc ? pc+2, if acc=0 jnz rn,address jump if register is not 0 machine code 1 0 1 0 0 a a a a a a a a a a a r0 1 0 1 0 1 a a a a a a a a a a a r1 1 1 0 1 1 a a a a a a a a a a a r4 description bits 0~10 of the program counter are replaced with the directly-specified address, bit 11 of the program counter and pa3 of the memory bank re - main, if the register is not 0. operation pc (bit 0~10) ? address, if rn 1 0; rn=r0,r1,r4 pc ? pc+2, if rn=0 jtmr address jump if time-out machine code 1 1 0 1 0 a a a a a a a a a a a description bits 0~10 of the program counter are replaced with the directly-specified address, bit 11 of the program counter and pa3 of the memory bank re - main, if the tf (timer flag) is set to 1. operation pc (bit 0~10) ? address, if tf=1 pc ? pc+2, if tf=0 jz a,address jump if accumulator is 0 machine code 1 0 1 1 0 a a a a a a a a a a a description bits 0~10 of the program counter are replaced with the directly-specified address, bit 11 of the program counter and pa3 of the memory bank re- main, if the accumulator is 0. operation pc (bit 0~10) ? address, if acc=0 pc ? pc+2, if acc 1 0 mov a,rn move register to accumulator machine code 0 0 1 0 n n n 1 description data in the working register "rn" is moved to the accumulator. operation acc ? rn; rn=r0, r1, r2, r3, r4, for n=0, 1, 2, 3, 4 mov a,tmrh move timer to accumulator machine code 0 0 1 1 1 0 1 1 description the high nibble data of timer counter is loaded to the accumulator. operation acc ? timer (high nibble)
ht13j0 23 may 19, 1999 mov a,tmrl move timer to accumulator machine code 0 0 1 1 1 0 1 0 description the low nibble data of timer counter is loaded to the accumulator. operation acc ? timer (low nibble) mov a,xh move immediate data to accumulator machine code 0 1 1 1 d d d d description the 4-bit data specified by code is loaded to the accumulator. operation acc ? xh mov a,[r1r0] move data memory to accumulator machine code 0 0 0 0 0 1 0 0 description data in the data memory specified by the register pair "r1,r0" is moved to the accumulator. operation acc ? m(r1,r0) mov a,[r3r2] move data memory to accumulator machine code 0 0 0 0 0 1 1 0 description data in the data memory specified by the register pair "r3,r2" is moved to the accumulator. operation acc ? m(r3,r2) mov r1r0,xxh move immediate data to r1 and r0 machine code 0 1 0 1 d d d d 0 0 0 0 d d d d description the 8-bit data specified by code are loaded to the working registers r1 and r0, the high nibble of the data is loaded to r1, and the low nibble of the data is loaded to r0. operation r1 ? xh (high nibble) r0 ? xh (low nibble) mov r3r2,xxh move immediate data to r3 and r2 machine code 0 1 1 0 d d d d 0 0 0 0 d d d d description the 8-bit data specified by code are loaded to the working register r3 and r2, the high nibble of the data is loaded to r3, and the low nibble of the data is loaded to r2. operation r3 ? xh (high nibble) r2 ? xh (low nibble)
ht13j0 24 may 19, 1999 mov r4,xh move immediate data to r4 machine code 0 1 0 0 0 1 1 0 0 0 0 0 d d d d description the 4-bit data specified by code are loaded to the working register r4. operation r4 ? xh mov rn,a move accumulator to register machine code 0 0 1 0 n n n 0 description data in the accumulator is moved to the working register "rn". operation rn ? acc; rn=r0, r1, r2, r3, r4, for n=0, 1, 2, 3, 4 mov tmrh,a move accumulator to timer machine code 0 0 1 1 1 1 0 1 description the contents of the accumulator is loaded to the high nibble of timer counter. operation timer (high nibble) ? acc mov tmrl,a move accumulator to timer machine code 0 0 1 1 1 1 0 0 description the contents of the accumulator is loaded to the low nibble of timer coun - ter. operation timer (low nibble) ? acc mov [r1r0],a move accumulator to data memory machine code 0 0 0 0 0 1 0 1 description data in the accumulator is moved to the data memory specified by the register pair "r1,r0". operation m(r1,r0) ? acc mov [r3r2],a move accumulator to data memory machine code 0 0 0 0 0 1 1 1 description data in the accumulator is moved to the data memory specified by the register pair "r3,r2". operation m(r3,r2) ? acc nop no operation machine code 0 0 1 1 1 1 1 0 description do nothing, but one instruction cycle is delayed.
ht13j0 25 may 19, 1999 or a,xh logical or immediate data to accumulator machine code 0 1 0 0 0 1 0 0 0 0 0 0 d d d d description data in the accumulator is logical or with the immediate data specified by code. operation acc ? acc "or" xh or a,[r1r0] logical or accumulator with data memory machine code 0 0 0 1 1 1 0 0 description data in the accumulator is logical or with the data memory addressed by the register pair "r1,r0". operation acc ? acc "or" m(r1,r0) or [r1r0],a logical or data memory with accumulator machine code 0 0 0 1 1 1 1 1 description data in the data memory addressed by the register pair "r1,r0" is logical or with the accumulator. operation m(r1,r0) ? m(r1,r0) "or" acc out pa,a output accumulator data to port a machine code 0 0 1 1 0 0 0 0 pa description the data in the accumulator is transferred to the port-a and latched. note: pa3 controls bit 13 of the program memory. be careful about pa3 when port a is changed. operation pa ? acc read mr0a read rom code of current page to m(r1,r0) and acc machine code 0 1 0 0 1 1 1 0 description the 8-bit rom code (current page) addressed by acc and r4 are moved to the data memory m(r1,r0) and accumulator. the high nibble of the rom code is loaded to m(r1,r0) and the low nibble of the rom code is loaded to the accumulator. the rom code address are specified as shown below: current page ? rom code address bit 12~8 acc ? rom code address bit 7~4 r4 ? rom code address bit 3~0 operation m(r1r0) ? rom code (high nibble) acc ? rom code (low nibble)
ht13j0 26 may 19, 1999 read r4a read rom code of current page to r4 and accumulator machine code 0 1 0 0 1 1 0 0 description the 8-bit rom code (current page) addressed by acc and m(r1,r0) are moved to the working register r4 and the accumulator. the high nibble of the rom code is loaded to r4 and the low nibble of the rom code is loaded to the accumulator. the rom code address are specified below: current page ? rom code address bit 12~8 acc ? rom code address bit 7~4 m(r1,r0) ? rom code address bit 3~0 operation r4 ? rom code (high nibble) acc ? rom code (low nibble) readf mr0a read rom code of page f to m(r1,r0) and acc machine code 0 1 0 0 1 1 1 1 description the 8-bit rom code (page f) addressed by acc and r4 are moved to the data memory m(r1,r0) and accumulator. the high nibble of the rom code is loaded to m(r1,r0) and the low nibble of the rom code is loaded to the accumulator. page f ? rom code address bit 12~8 are "pa3 1111" acc ? rom code address bit 7~4 r4 ? rom code address bit 3~0 operation m(r1,r0) ? high nibble of rom code (page f) acc ? low nibble of rom code (page f) readf r4a read rom code of page f to r4 and accumulator machine code 0 1 0 0 1 1 0 1 description the 8-bit rom code (page f) addressed by acc and m(r1,r0) are moved to the working register r4 and the accumulator. the high nibble of the rom code is loaded to r4 and the low nibble of the rom code is loaded to the accumulator. page f ? rom code address bit 12~8 are "pa3 1111" acc ? rom code address bit 7~4 m(r1,r0) ? rom code address bit 3~0 operation r4 ? high nibble of rom code (page f) acc ? low nibble of rom code (page f) ret return from subroutine or interrupt machine code 0 0 1 0 1 1 1 0 description the program counter bits 0~11 are restored from the stack. operation pc ? stack
ht13j0 27 may 19, 1999 reti return from interrupt subroutine machine code 0 0 1 0 1 1 1 1 description the program counter bits 0~11 are restored from the stack. the carry flag before entering interrupt service routine is restored. operation pc ? stack c ? c (before interrupt service routine) rl a rotate accumulator left machine code 0 0 0 0 0 0 0 1 description the contents of the accumulator are rotated left 1 bit. bit 3 is rotated to bit 0 and carry flag. operation an+1 ? an; an: accumulator bit n (n=0, 1, 2) a0 ? a3 c ? a3 rlc a rotate accumulator left through carry machine code 0 0 0 0 0 0 1 1 description the contents of the accumulator are rotated left 1 bit. bit 3 replaces the carry bit; the carry bit is rotated into the bit 0 position. operation an+1 ? an; an: accumulator bit n (n=0, 1, 2) a0 ? c c ? a3 rr a rotate accumulator right machine code 0 0 0 0 0 0 0 0 description the contents of the accumulator are rotated right 1 bit. bit 0 is rotated to bit 3 and carry flag. operation an ? an+1; an: accumulator bit n (n=0, 1, 2) a3 ? a0 c ? a0 rrc a rotate accumulator right through carry machine code 0 0 0 0 0 0 1 0 description the contents of the accumulator are rotated right 1 bit. bit 0 replaces the carry bit; the carry bit is rotated into the bit 3 position. operation an ? an+1; an: accumulator bit n (n=0,1,2) a3 ? c c ? a0
ht13j0 28 may 19, 1999 sbc a,[r1r0] subtract data memory contents and carry from acc machine code 0 0 0 0 1 0 1 0 description the contents of the data memory addressed by the register pair "r1,r0" and carry are subtracted from the accumulator. carry is affected. operation acc ? acc+m(r1,r0) +cf sound a active sound channel with accumulator machine code 0 1 0 0 1 0 1 1 description the activated sound begins playing in accordance with the contents of the accumulator when the specified sound channel is matched. sound loop turn on sound repeat mode machine code 0 1 0 0 1 0 0 1 description the activated sound plays repeatedly. sound off turn off sound machine code 0 1 0 0 1 0 1 0 description the singing sound will terminate immediately. sound one turn on sound one mode machine code 0 1 0 0 1 0 0 0 description the activated sound plays only one time. sound n active sound channel n machine code 0 0 0 0 n n n n 0 1 0 0 0 1 0 1 description the specified sound begins playing and overwriting the previous singing sound. (n=0~15) stc set carry flag machine code 0 0 1 0 1 0 1 1 description the carry flag is set to1. operation c ? 1 sub a,xh subtract immediate data from accumulator machine code 0 1 0 0 0 0 0 1 0 0 0 0 d d d d description the specified data is subtracted from the accumulator. carry is affected. operation acc ? acc+xh +1
ht13j0 29 may 19, 1999 sub a,[r1r0] subtract data memory contents from accumulator machine code 0 0 0 0 1 0 1 1 description the contents of the data memory addressed by the register pair "r1,r0" is subtracted from the accumulator. carry is affected. operation acc ? acc+m(r1,r0) +1 timer off set timer to stop counting machine code 0 0 1 1 1 0 0 1 description the timer stops counting, when the "timer off" instruction is exe - cuted. timer on set timer to start counting machine code 0 0 1 1 1 0 0 0 description the timer starts counting, when the "timer on" instruction is exe - cuted. timer xxh set immediate data to timer counter machine code 0 1 0 0 0 1 1 1 d d d d d d d d description the 8-bit data specified by code is loaded to the timer counter. operation timer ? xxh xor a,xh logical xor immediate data to accumulator machine code 0 1 0 0 0 0 1 1 0 0 0 0 d d d d description data in the accumulator is exclusive-or with the immediate data speci- fied by code. operation acc ? acc "xor" xh xor a,[r1r0] logical xor accumulator with data memory machine code 0 0 0 1 1 0 1 1 description data in the accumulator is exclusive-or with the data memory ad- dressed by the register pair "r1,r0". operation acc ? acc "xor" m(r1,r0) xor [r1r0],a logical xor data memory with accumulator machine code 0 0 0 1 1 1 1 0 description data in the data memory addressed by the register pair "r1,r0" is logi - cally exclusive-or with the accumulator. operation m(r1,r0) ? m(r1,r0) "xor" acc
ht13j0 30 may 19, 1999 copyright 1999 by hol tek semiconductor inc. the information appearing in this data sheet is believed to be accurate at the time of publication. however, holtek assumes no responsibility arising from the use of the specifications described. the applications mentioned herein are used solely for the purpose of illustration and holtek makes no warranty or representation that such applications will be suitable without further modification, nor recommends the use of its products for application that may pres - ent a risk to human life due to malfunction or otherwise. holtek reserves the right to alter its products without prior notification. for the most up-to-date information, please visit our web site at http://www.holtek.com.tw. holtek semiconductor inc. (headquarters) no.3 creation rd. ii, science-based industrial park, hsinchu, taiwan, r.o.c. tel: 886-3-563-1999 fax: 886-3-563-1189 holtek semiconductor inc. (taipei office) 5f, no.576, sec.7 chung hsiao e. rd., taipei, taiwan, r.o.c. tel: 886-2-2782-9635 fax: 886-2-2782-9636 fax: 886-2-2782-7128 (international sales hotline) holtek microelectronics enterprises ltd. rm.711, tower 2, cheung sha wan plaza, 833 cheung sha wan rd., kowloon, hong kong tel: 852-2-745-8288 fax: 852-2-742-8657

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